In semiconductor processing, structures are commonly formed on a substrate through lithographic processes. In such processes, a layer of photoresist is deposited on a substrate and is patterned by exposing it to a source of radiation through a mask or reticle. Solubility differences between the exposed and unexposed portion of the photoresist may then be exploited to selectively remove the undesired portion of the photoresist, thus leaving a desired pattern of photoresist on the substrate. The pattern formed in the photoresist layer may then be transferred to the underlying layer through etching. Alternatively, the photoresist layer can be used to block dopant implantation into portions of the underlying layer or to retard reaction of the protected portions of the underlying layer. Thereafter, the remaining portions of the photoresist layer can be stripped.
The ongoing trend in the semiconductor arts toward smaller feature sizes and higher structure densities has created a corresponding need to increase the resolution capability of lithography processes. To that end, the use of actinic radiation having shorter wavelengths has become more common.
As the critical dimensions of features that are formed using ultra thin resists become smaller, the line edge roughness (LER) of the photoresist tends to increase. Since this roughness is passed on to the features defined by the photomask, when LER becomes sufficiently high, device performance is adversely affected. Hence, the need for further reduction in critical dimensions in semiconductor devices has created a need for further reductions in LER.
Accordingly, there exists a need in the art for improved lithography processes that provide for greater control of LER. There is also a need in the art for lithography processes that can produce semiconductor devices with smaller critical dimensions. These and other needs may be met by the devices and methodologies described herein.